Recent advances in the field of semiconductor integrated circuits have brought about higher levels of integration. Semiconductor manufacturing process advancements are driving the corresponding geometric dimensions for semiconductor devices to decreasingly smaller values. As semiconductor device dimensions shrink, the number of devices per unit area of semiconductor die grows. Given higher device densities within semiconductor die, a greater opportunity exists that devices, which must interface to one another, operate at incompatible drive levels.
Incompatible drive levels may also pose integration problems when the interface circuitry of two devices do not share the same semiconductor die. A configuration device, for example, implemented to download configuration data to a programmable logic circuit, may be operating at a much higher potential than the programmable logic circuit. In such an instance, the voltage magnitude of the configuration data generated by the configuration device may be at levels that are more than twice the voltage magnitudes required by the programmable logic circuit. As such, an intermediate voltage translation device is necessary to translate the configuration data from its relatively high voltage levels, to the relatively low voltage levels that are compatible with the programmable logic circuit.
In the prior art, pass transistors are often employed to perform the voltage translation that is required between communication devices operating at different voltage levels. In particular, the symmetrical properties of Field Effect Transistors (FET) are often employed, such that logic values at a first voltage level are presented to a first conductor of the FET and then translated to logic values at a second voltage level at a second conductor of the FET. Such a translation circuit, however, also requires fairly sophisticated bias control circuitry, in order to maintain a proper bias voltage at the control terminal of the FET to allow the logic values to properly propagate through the FET.
A further disadvantage of the prior art translation circuits may result from their lack of current drive capability, as the level of current provided by the prior art pass transistor may be limited by its geometry. Furthermore, in order to implement differential translation capability, two pass transistors are required, each requiring separate bias control circuitry.